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LTC3633 1 3633f n 3.6v to 15v input voltage range n 3a output current per channel n up to 95% ef? ciency n low duty cycle operation: 5% at 2.25mhz n selectable 0/180 phase shift between channels n adjustable switching frequency: 500khz to 4mhz n external frequency synchronization n current mode operation for excellent line and load transient response n 0.6v reference allows low output voltages n user selectable burst mode ? operation or forced continuous operation n output voltage tracking and soft-start capability n short-circuit protected n overvoltage input and overtemperature protection n low power 2.5v linear regulator output n power good status outputs n available in (4mm 5mm) qfn-28 and 28-lead tssop packages typical application description dual channel 3a, 15v monolithic synchronous step-down regulator the ltc ? 3633 is a high ef? ciency, dual-channel monolithic synchronous buck regulator using a controlled on-time, current mode architecture, with phase lockable switching frequency. the two channels can run 180 out of phase, which relaxes the requirements for input and output ca- pacitance. the operating supply voltage range is from 3.6v to 15v, making it suitable for dual cell lithium-ion batteries as well as point of load power supply applications from a 12v or 5v supply. the operating frequency is programmable and synchroniz- able from 500khz to 4mhz with an external resistor. the high frequency capability allows the use of small surface mount inductors and capacitors. the unique constant frequency/controlled on-time architecture is ideal for high step-down ratio applications that operate at high frequency while demanding fast transient response. an internal phase lock loop servos the on-time of the internal one-shot timer to match the frequency of the internal clock or an applied external clock. the LTC3633 can select between forced continuous mode and high ef? ciency burst mode operation. features applications n distributed power systems n battery powered instruments n point of load power supplies ef? ciency vs load current l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611. 1 0 efficiency (%) 10 30 40 50 70 100 10000 3633 ta01b 20 80 100 90 60 10 1000 v out = 5v v out = 3.3v load current (ma) burst mode operation v in = 12v run1 run2 trackss2 pgood2 LTC3633 boost2 0.1f 1.5h 73.2k 10k sw2 v on2 v in2 pgnd sgnd v in1 v fb2 phmode trackss1 pgood1 boost1 sw1 v on1 v fb1 22f v out2 5v at 3a 0.1f 1h 45.3k 10k 22f v out1 3.3v at 3a v in 3.6v to 15v 47f x2 mode/sync v2p5 rt ith1 ith2 intv cc 2.2f 3633 ta01a
LTC3633 2 3633f pin configuration absolute maximum ratings v in1 , v in2 ................................................... C0.3v to 16v v in1 , v in2 transient ...................................................18v pgood1, pgood2, v on1 , v on2 ................. C0.3v to 16v boost1, boost2 ................................... C0.3v to 19.6v boost1-sw1, boost2-sw2 ................... C0.3v to 3.6v v2p5, intv cc , trackss1, trackss2 ...... C0.3v to 3.6v ith1, ith2, rext, mode/sync .... C0.3v to intv cc + 0.3v (note 1) order information lead free finish tape and reel part marking* package description temperature range LTC3633eufd#pbf LTC3633eufd#trpbf 3633 28-lead (4mm 5mm) plastic qfn C40c to 125c LTC3633iufd#pbf LTC3633iufd#trpbf 3633 28-lead (4mm 5mm) plastic qfn C40c to 125c LTC3633efe#pbf LTC3633efe#trpbf LTC3633fe 28-lead plastic tssop C40c to 125c LTC3633ife#pbf LTC3633ife#trpbf LTC3633fe 28-lead plastic tssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a la bel on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ v fb1 , v fb2 , phmode. .................. C0.3v to intv cc + 0.3v run1, run2 .................................... C0.3v to v in + 0.3v sw1, sw2 ....................................... C0.3v to v in + 0.3v sw source and sink current (dc) (note 2) ................3a operating junction temperature range (note 3) .................................................. C40c to 125c storage temperature range ................... C65c to 125c 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 pgood1 phmode run1 mode/sync rt run2 sgnd pgood2 v in1 v in1 boost1 intv cc v2p5 boost2 v in2 v in2 v fb1 trackss1 ith1 v on1 sw1 sw1 v fb2 trackss2 ith2 v on2 sw2 sw2 7 17 18 19 20 21 22 16 8 15 29 pgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ith1 trackss1 v fb1 pgood1 phmode run1 mode/sync rt run2 sgnd pgood2 v fb2 trackss2 ith2 v on1 sw1 sw1 v in1 v in1 boost1 intv cc v2p5 boost2 v in2 v in2 sw2 sw2 v on2 29 pgnd t jmax = 125c, ja = 43c/w exposed pad (pin 29) is pgnd, must be soldered to pcb t jmax = 125c, ja = 25c/w exposed pad (pin 29) is pgnd, must be soldered to pcb
LTC3633 3 3633f electrical characteristics symbol parameter conditions min typ max units v in supply range l 3.6 15 v i q input dc supply current (v in1 + v in2 ) both channels active (note 5) sleep current shutdown mode = 0v mode = intv cc , v fb1 , v fb2 > 0.6 run = 0v 1.3 500 13 ma a a v fb feedback reference voltage l 0.594 0.6 0.606 v v line_reg reference voltage line regulation v in = 3.6v to 15v 0.02 %/v v load_reg output voltage load regulation ith = 0.8v to 1.6v 0.05 % i fb feedback pin input current 30 na g m(ea) error ampli? er transconductance ith = 1.2v 1.8 ms t on minimum on time v on = 1v, v in = 4v 20 ns t off minimum off time v in = 6v 40 60 ns f osc oscillator frequency v rt = intv cc rt = 160k rt = 80k 1.4 1.7 3.4 2 2 4 2.6 2.3 4.6 mhz mhz mhz i lim valley switch current limit channel 1 (3a) channel 2 (3a) 2.6 2.6 3.5 3.5 4.5 4.5 a a r ds(on) channel 1 top switch on-resistance bottom switch on-resistance channel 2 top switch on-resistance bottom switch on-resistance 130 65 130 65 m m m m i sw(lkg) switch leakage current v in = 15v, v run = 0v 0.01 1 a v vin-ov v in overvoltage lockout threshold v in rising v in falling 16.8 15.8 17.5 16.5 18 17 v v intv cc voltage 3.6v < v in < 15v, 0ma load 3.1 3.3 3.5 v intv cc load regulation 0ma to 50ma load, v in = 4v to 15v 0.7 % run threshold rising run threshold falling l l 1.18 0.98 1.22 1.01 1.26 1.04 v v run leakage current v in = 15v 0 3 a v2p5 voltage i load = 0ma to 10ma l 2.46 2.5 2.54 v pgood good-to-bad threshold v fb rising v fb falling 8 C8 10 C10 % % pgood bad-to-good threshold v fb falling v fb rising C3 3 C5 5 % % r pgood pgood pull-down resistance 10ma load 15 t pgood power good filter time 20 40 s t ss internal soft-start time 400 700 s v fb during tracking trackss = 0.3v 0.28 0.3 0.315 v i trackss trackss pull-up current 1.4 a v phmode phmode threshold voltage phmode v ih phmode v il 1 0.3 v v the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t j = 25c. v in = 12v, intv cc = 3.3v, unless otherwise noted.
LTC3633 4 3633f electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: guaranteed by long term current density limitations. note 3: the LTC3633e is guaranteed to meet speci? ed performance from 0c to 85c. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3633i is guaranteed to meet symbol parameter conditions min typ max units v mode/sync mode/sync threshold voltage mode v ih mode v il 1 0.4 v v sync threshold voltage sync v ih 0.95 v i mode mode/sync input current mode = 0v mode = intv cc 1.5 C1.5 a a the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t j = 25c. v in = 12v, intv cc = 3.3v, unless otherwise noted. speci? cations over the full C40c to 125c operating junction temperature range note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 5: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency.
LTC3633 5 3633f typical performance characteristics ef? ciency vs load current ef? ciency vs input voltage burst mode operation load regulation oscillator frequency vs temperature ef? ciency vs load current burst mode operation ef? ciency vs load current forced continuous mode operation ef? ciency vs load current t j = 25c, v in = 12v, f sw = 1mhz, l = 1h unless otherwise noted. oscillator internal set frequency vs temperature reference voltage vs temperature 1 0 efficiency (%) 10 30 40 50 70 100 10000 3633 g01 20 80 100 90 60 10 1000 v in = 4v v in = 8v v in = 12v load current (ma) v out = 1.8v 1 0 efficiency (%) 10 30 40 50 70 100 10000 3633 g02 20 80 100 90 60 10 1000 v in = 4v v in = 8v v in = 12v load current (ma) v out = 1.8v 1 0 efficiency (%) 10 30 40 50 70 100 10000 3633 g03 20 80 100 90 60 10 1000 v out = 5v v out = 3.3v load current (ma) burst mode operation forced continuous operation 4 efficiency (%) 65 70 75 85 8 16 3633 g05 60 90 100 95 80 6101214 i load = 10ma i load = 100ma i load = 1a i load = 3a input voltage (v) 0.1 1 0 efficiency (%) 10 30 40 50 70 100 10000 3633 g04 20 80 100 90 60 10 1000 load current (ma) v in = 4v v in = 8v v in = 12v v in = 15v C50 v fb (v) 0.597 0.599 50 150 3633 g06 0.595 0.601 0.605 0.603 25 C25 0 75 100 125 temperature (c) 0 v out /v out (%) 0.0 0.4 1.5 3 3633 g07 C0.4 0.8 1.6 1.2 1 0.5 2 2.5 i load (a) burst mode operation forced continuous C50 frequency variation (%) C8 C6 C4 C2 0 2 4 6 8 25 125 3633 g08 C10 10 0 C25 50 75 100 temperature (c) C50 frequency (mhz) 1.6 1.8 2.0 2.2 2.4 25 125 3633 g09 1.4 2.6 0 C25 50 75 100 temperature (c) r t = intv cc
LTC3633 6 3633f burst mode operation internal mosfet r ds(on) vs temperature quiescent current vs v in burst mode operation switch leakage vs temperature valley current limit vs temperature track pull-up current vs temperature typical performance characteristics shutdown current vs v in v2p5 load regulation load step 4 i q (a) 100 200 300 500 8 16 3633 g11 0 600 800 700 400 6101214 t a = 90c t a = 25c t a = C40c v in (v) 4 i q (a) 2 4 6 10 8 16 3633 g12 0 12 20 16 18 14 8 6101214 v in (v) C50 leakage current (na) 1000 2000 3000 5000 0 125 100 3633 g13 0 6000 7000 4000 C25 25 50 75 temperature (c) main switch synchronous switch t j = 25c, v in = 12v, f sw = 1mhz, l = 1h unless otherwise noted. temperature (c) C50 1.4 1.6 2.0 25 75 3633 g15 1.2 1.0 C25 0 50 100 125 0.8 0.6 1.8 i track (a) C50 i lim (a) 3.4 3.5 50 3633 g14 3.3 3.7 3.6 3.9 3.8 25 C25 0 75 100 125 temperature (c) 0 v2p5(v) 2.496 2.498 6 3633 g16 2.494 2.502 2.500 2.506 2.504 4 2810 i load (ma) i l 1a/div sw 10v/div 5s/div 3633 g17 v out 50mv/div v out = 1.8v i load = 100ma i l 2a/div 20s/div 3633 g18 v out ac-coupled 100mv/div v out = 1.8v i load = 100ma to 3a c ith = 220pf r ith = 13k C50 r ds(on) () 20 40 60 80 100 120 140 25 125 3633 g10 0 160 0 C25 50 75 100 temperature (c) top switch bottom switch
LTC3633 7 3633f typical performance characteristics start-up into prebiased output (forced continuous mode) load step (internal compensation) start-up into prebiased output (burst mode operation) start-up (burst mode operation) t j = 25c, v in = 12v, f sw = 1mhz, l = 1h unless otherwise noted. start-up (forced continuous mode) i l 2a/div 20s/div 3633 g19 v out ac-coupled 100mv/div v out = 1.8v i load = 100ma to 3a ith = intv cc i l 2a/div 400s/div 3633 g20 run 2v/div v out 1v/div c ss = 4.7nf i load = 150ma i l 1a/div 400s/div 3633 g21 run 2v/div v out 1v/div c ss = 4.7nf i load = 150ma i l 1a/div 200s/div 3633 g22 run 2v/div v out 1.8v 1v/div i load = 0ma i l 2a/div 1ms/div 3633 g22 run 2v/div v out 1.8v 1v/div i load = 0ma
LTC3633 8 3633f pin functions pgood1 (pin 1/pin 4): channel 1 open-drain power good output pin. pgood1 is pulled to ground when the voltage on the v fb1 pin is not within 8% (typical) of the internal 0.6v reference. pgood1 becomes high imped- ance once the v fb1 pin returns to within 5% (typical) of the internal reference. phmode (pin 2/pin 5): phase select input. tie this pin to ground to force both channels to switch in phase. tie this pin to intv cc to force both channels to switch 180 out of phase. do not ? oat this pin. run1 (pin 3/pin 6): channel 1 regulator enable pin. enables channel 1 operation by tying run above 1.22v. tying it below 1v places the part into shutdown. do not ? oat this pin. mode/sync (pin 4/pin 7): mode select and external synchronization input. tie this pin to ground to force continuous synchronous operation at all output loads. floating this pin or tying it to intv cc enables high ef? ciency burst mode operation at light loads. drive this pin with a clock to synchronize the LTC3633 switching. an internal phase-locked loop will force the bottom power nmoss turn on signal to be synchronized with the rising edge of the clkin signal. when this pin is driven with a clock, forced continuous mode is automatically selected. rt (pin 5/pin 8): oscillator frequency program pin. connect an external resistor (between 80k to 640k) from this pin to sgnd in order to program the frequency from 500khz to 4mhz. when rt is tied to intv cc , the switching frequency will default to 2mhz. run2 (pin 6/pin 9): channel 2 regulator enable pin. enables channel 2 operation by tying run above 1.22v. tying it below 1v places the part into shutdown. do not ? oat this pin. sgnd (pin 7/pin 10): signal ground pin. this pin should have a low noise connection to reference ground. the feedback resistor network, external compensation network, and rt resistor should be connected to this ground. pgood2 (pin 8/pin 11): channel 2 open-drain power good output pin. pgood2 is pulled to ground when the voltage on the v fb2 pin is not within 8% (typical) of the internal 0.6v reference. pgood2 becomes high imped- ance once the v fb2 pin returns to within 5% (typical) of the internal reference. v fb2 (pin 9/pin 12): channel 2 output feedback voltage pin. input to the error ampli? er that compares the feedback voltage to the internal 0.6v reference voltage. connect this pin to a resistor divider network to program the desired output voltage. trackss2 (pin 10/pin 13): output tracking and soft-start input pin for channel 2. forcing a voltage below 0.6v on this pin bypasses the internal reference input to the error ampli? er. the LTC3633 will servo the fb pin to the track voltage under this condition. above 0.6v, the tracking func- tion stops and the internal reference resumes control of the error ampli? er. an internal 1.4a pull up current from intv cc allows a soft start function to be implemented by connecting a capacitor between this pin and sgnd. ith2 (pin 11/pin 14): channel 2 error ampli? er output and switching regulator compensation pin. connect this pin to appropriate external components to compensate the regulator loop frequency response. connect this pin to intv cc to use the default internal compensation. v on2 (pin 12/pin 15): on-time voltage input for chan- nel 2. this pin sets the voltage trip point for the on-time comparator. tying this pin to the output voltage makes the on-time proportional to v out2 when v out2 < 6v. when v out2 > 6v, switching frequency may become higher than the set frequency. the pin impedance is nominally 180k. sw2 (pins 13, 14/pins 16, 17): channel 2 switch node connection to external inductor. voltage swing of sw is from a diode voltage drop below ground to v in . v in2 (pins 15, 16/pins 18, 19): power supply input for channel 2. input voltage to the on chip power mosfets on channel 2. this input is capable of operating from a different supply voltage than v in1 . boost2 (pin 17/pin 20): boosted floating driver supply for channel 2. the (+) terminal of the bootstrap capacitor connects to this pin while the (C) terminal connects to the sw pin. the normal operation voltage swing of this pin ranges from a diode voltage drop below intv cc up to v in +intv cc . (qfn/tssop)
LTC3633 9 3633f pin functions v2p5 (pin 18/pin 21): 2.5v regulator output. outputs a regulated 2.5v supply voltage capable of supplying 10ma. bypass this pin with a minimum of 1f low esr ceramic capacitor. tie this pin to intv cc when this output is not being used in the application. intv cc (pin 19/pin 22): internal 3.3v regulator output. the internal power drivers and control circuits are powered from this voltage. decouple this pin to power ground with a minimum of 1f low esr ceramic capacitor. boost1 (pin 20/pin 23): boosted floating driver supply for channel 1. the (+) terminal of the bootstrap capacitor connects to this pin while the (C) terminal connects to the sw pin. the normal operation voltage swing of this pin ranges from a diode voltage drop below intv cc up to v in + intv cc . v in1 (pins 21,22/pins 24, 25): power supply input for channel 1. input voltage to the on chip power mosfets on channel 1. the internal ldo for intv cc is powered off of this pin. sw1 (pins 23,24/pins 26, 27): channel 1 switch node connection to external inductor. voltage swing of sw is from a diode voltage drop below ground to v in . v on1 (pin 25/pin 28): on-time voltage input for chan- nel 1. this pin sets the voltage trip point for the on-time comparator. tying this pin to the regulated output volt- age makes the on-time proportional to v out1 when v out1 < 6v. when v out1 > 6v, switching frequency may become higher than the set frequency. the pin impedance is nominally 180k. ith1 (pin 26/pin 1): channel 1 error ampli? er output and switching regulator compensation pin. connect this pin to appropriate external components to compensate the regulator loop frequency response. connect this pin to intv cc to use the default internal compensation. trackss1 (pin 27/pin 2): output tracking and soft-start input pin for channel 1. forcing a voltage below 0.6v on this pin bypasses the internal reference input to the error ampli? er. the LTC3633 will servo the fb pin to the track voltage. above 0.6v, the tracking function stops and the internal reference resumes control of the error ampli? er. an internal 1.4a pull up current from intv cc allows a soft-start function to be implemented by connecting a capacitor between this pin and sgnd. v fb1 (pin 28/pin 3): channel 1 output feedback voltage pin. input to the error ampli? er that compares the feedback voltage to the internal 0.6v reference voltage. connect this pin to a resistor divider network to program the desired output voltage. pgnd (exposed pad pin 29/exposed pad pin 29): power ground pin. the (C) terminal of the input bypass capaci- tor, c in , and the (C) terminal of the output capacitor, c out , should be tied to this pin with a low impedance connec- tion. this pin must be soldered to the pcb to provide low impedance electrical contact to power ground and good thermal contact to the pcb.
LTC3633 10 3633f block diagram 0.72v 6v v on v in c in 1.25v intv cc intv cc run ? + + ith pgood a v = 1 t on = v von i ion i on v in i cmp i rev osc1 180k on tg m1 boost sw pgnd fb sense C sense + 1.4a 0.6v ref m2 bg switch logic and anti- shoot through i on controller comp select osc osc pll-sync phase select mode select r sq c boost l1 c out ? ? + ? + ea c c1 r c 0.648v 0.552v track 0.48v at start-up 0.10v after start-up channel 1 channel 2 (same as channel 1) 3633 bd osc1 osc2 rt r rt phmode r2 r1 internal soft-start ideal diodes ? ? + + ? + burst fc 3.3v reg pv in1 mode/sync trackss v2p5 sgnd intv cc c vcc 2.5v reg c ss run run 0v uv ss
LTC3633 11 3633f operation the LTC3633 is a dual-channel, current mode monolithic step down regulator capable of providing 3a of output current from each channel. its unique controlled on-time architecture allows extremely low step-down ratios while maintaining a constant switching frequency. each channel is enabled by raising the voltage on the run pin above 1.22v nominally. main control loop in normal operation, the internal top power mosfet is turned on for a ? xed interval determined by a ? xed one- shot timer (on signal in block diagram). when the top power mosfet turns off, the bottom power mosfet turns on until the current comparator i cmp trips, thus restarting the one shot timer and initiating the next cycle. inductor current is measured by sensing the voltage drop across the sw and pgnd nodes of the bottom power mosfet. the voltage on the ith pin sets the comparator threshold corresponding to inductor valley current. the error ampli- ? er ea adjusts this ith voltage by comparing an internal 0.6v reference to the feedback signal v fb derived from the output voltage. if the load current increases, it causes a drop in the feedback voltage relative to the internal refer- ence. the ith voltage then rises until the average inductor current matches that of the load current. the operating frequency is determined by the value of the rt resistor, which programs the current for the internal oscillator. an internal phase-locked loop servos the switch- ing regulator on-time to track the internal oscillator edge and force a constant switching frequency. a clock signal can be applied to the mode/sync pin to synchronize the switching frequency to an external source. the regulator defaults to forced continuous operation once the clock signal is applied. at light load currents, the inductor current can drop to zero and become negative. in burst mode operation, a current reversal comparator (i rev ) detects the negative inductor current and shuts off the bottom power mosfet, result- ing in discontinuous operation and increased ef? ciency. both power mosfets will remain off until the ith volt- age rises above the zero current level to initiate another cycle. during this time, the output capacitor supplies the load current and the part is placed into a low current sleep mode. discontinuous mode operation is disabled by tying the mode/sync pin to ground, which forces continuous synchronous operation regardless of output load current. power good status output the pgood open-drain output will be pulled low if the regulator output exits a 8% window around the regulation point. this condition is released once regulation within a 5% window is achieved. to prevent unwanted pgood glitches during transients or dynamic v out changes, the LTC3633 pgood falling edge includes a ? lter time of ap- proximately 40s. v in overvoltage protection in order to protect the internal power mosfet devices against transient voltage spikes, the LTC3633 constantly monitors each v in pin for an overvoltage condition. when v in rises above 17.5v, the regulator suspends operation by shutting off both power mosfets on the correspond- ing channel. once v in drops below 16.5v, the regulator immediately resumes normal operation. the regulator does not execute its soft-start function when exiting an overvoltage condition. out-of-phase operation tying the phmode pin high sets the sw2 falling edge to be 180 out of phase with the sw1 falling edge. there is a signi? cant advantage to running both channels out of phase. when running the channels in phase, both top-side mosfets are on simultaneously, causing large current pulses to be drawn from the input capacitor and supply at the same time. when running the LTC3633 channels out of phase, the large current pulses are interleaved, effectively reducing the amount of time the pulses overlap. thus, the total rms input current is decreased, which both relaxes the capacitance requirements for the v in bypass capacitors and reduces the voltage noise on the supply line. one potential disadvantage to this con? guration occurs when one channel is operating at 50% duty cycle. in this situation, switching noise can potentially couple from one channel to the other, resulting in frequency jitter on one or both channels. this effect can be mitigated with a well designed board layout.
LTC3633 12 3633f applications information a general LTC3633 application circuit is shown on the ? rst page of this data sheet. external component selection is largely driven by the load requirement and switching frequency. component selection typically begins with the selection of the inductor l and resistor r t . once the inductor is chosen, the input capacitor, c in , and the out- put capacitor, c out , can be selected. next, the feedback resistors are selected to set the desired output voltage. finally, the remaining optional external components can be selected for functions such as external loop compensation, track/soft-start, v in uvlo, and pgood. programming switching frequency selection of the switching frequency is a trade-off between ef? ciency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves ef? ciency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. connecting a resistor from the rt pin to sgnd programs the switching frequency (f) between 500khz and 4mhz according to the following formula: r rt = 3.2e 11 f where r rt is in and f is in hz. when rt is tied to intv cc , the switching frequency will default to approximately 2mhz, as set by an internal re- sistor. this internal resistor is more sensitive to process and temperature variations than an external resistor (see typical performance characteristics) and is best used for applications where switching frequency accuracy is not critical. inductor selection for a given input and output voltage, the inductor value and operating frequency determine the inductor ripple current. more speci? cally, the inductor ripple current decreases with higher inductor value or higher operating frequency according to the following equation: i l = v out f? l 1C v out v i n where i l = inductor ripple current, f = operating frequency and l = inductor value. a trade-off between component size, ef? ciency and operating frequency can be seen from this equation. accepting larger values of i l allows the use of lower value inductors but results in greater inductor core loss, greater esr loss in the output capacitor, and larger output voltage ripple. generally, highest ef? ciency operation is obtained at low operating frequency with small ripple current. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest v in . exceeding 60% of i out(max) is not recommended. to guarantee that ripple current does not exceed a speci? ed maximum, the inductance should be chosen according to: l = v out f? i l(max ) 1C v out v in(max ) once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a ? xed inductor value, but is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire, leading to increased dcr and copper loss. 0 frequency (khz) 1000 2000 3000 5000 200 700 600 3633 f01 0 6000 4000 100 300 400 500 r t resistor (k) figure 1. switching frequency vs r t
LTC3633 13 3633f applications information ferrite designs exhibit very low core loss and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura- tion. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current, so it is important to ensure that the core will not saturate. different core materials and shapes will change the size/cur- rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated ? eld/emi requirements. table 1 gives a sampling of available surface mount inductors. table 1. inductor selection table inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) wrth electronik we-hc 744312 series 0.25 0.47 0.72 1.0 1.5 2.5 3.4 7.5 9.5 10.5 18 16 12 11 9 7 7.7 3.8 vishay ihlp-2020bz-01 series 0.22 0.33 0.47 0.68 1 5.2 8.2 8.8 12.4 20 15 12 11.5 10 7 5.2 5.5 2 toko fdv0620 series 0.20 0.47 1.0 4.5 8.3 18.3 12.4 9.0 5.7 7 7.7 2.0 coilcraft d01813h series 0.33 0.56 1.2 4 10 17 10 7.7 5.3 6 8.9 5.0 tdk rlf7030 series 1.0 1.5 8.8 9.6 6.4 6.1 6.9 7.3 3. 2 c in and c out selection the input capacitance, c in , is needed to ? lter the trapezoi- dal wave current at the drain of the top power mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current is recommended. the maximum rms current is given by: ii vvv v rms out max out in out in = ? () () this formula has a maximum at v in = 2v out , where i rms ? i out /2. this simple worst case condition is com- monly used for design because even signi? cant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further de- rate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, suf? cient bulk input capacitance is needed to minimize transient effects during output load changes. even though the LTC3633 design includes an overvoltage protection circuit, care must always be taken to ensure input voltage transients do not pose an overvoltage hazard to the part. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, v out , is approximated by: v out < i l esr + 1 8?f?c ou t when using low-esr ceramic capacitors, it is more useful to choose the output capacitor value to ful? ll a charge stor- age requirement. during a load step, the output capacitor
LTC3633 14 3633f applications information must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically, 3 to 4 cycles are required to respond to a load step, but only in the ? rst cycle does the output drop linearly. the output droop, v droop , is usually about 3 times the linear drop of the ? rst cycle. thus, a good place to start is with the output capacitor size of approximately: c out 3? i out f?v droop though this equation provides a good approximation, more capacitance may be required depending on the duty cycle and load step requirements. the actual v droop should be veri? ed by applying a load step to the output. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are available in small case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, due to the self-resonant and high- q characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. for a more detailed discussion, refer to application note 88. when choosing the input and output ceramic capacitors, choose the x5r and x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. intv cc regulator bypass capacitor an internal low dropout (ldo) regulator produces the 3.3v supply that powers the internal bias circuitry and drives the gate of the internal mosfet switches. the intv cc pin connects to the output of this regulator and must have a minimum of 1f ceramic decoupling capaci- tance to ground. the decoupling capacitor should have low impedance electrical connections to the intv cc and pgnd pins to provide the transient currents required by the LTC3633. this supply is intended only to supply ad- ditional dc load currents as desired and not intended to regulate large transient or ac behavior, as this may impact LTC3633 operation. boost capacitor the LTC3633 uses a bootstrap circuit to create a voltage rail above the applied input voltage v in . speci? cally, a boost capacitor, c boost , is charged to a voltage approximately equal to intv cc each time the bottom power mosfet is turned on. the charge on this capacitor is then used to supply the required transient current during the remainder of the switching cycle. when the top mosfet is turned on, the boost pin voltage will be equal to approximately v in + 3.3v. for most applications, a 0.1f ceramic capacitor closely connected between the boost and sw pins will provide adequate performance. low power 2.5v linear regulator the v2p5 pin can be used as a low power 2.5v regulated rail. this pin is the output of a 10ma linear regulator powered from the intv cc pin. note that the power from v2p5 eventually comes from v in1 since the intv cc power is supplied from v in1 . when using this output, this pin must be bypassed with a 1f ceramic capacitor. if this output is not being used, it is recommended to short this output to intv cc to disable the regulator.
LTC3633 15 3633f figure 2. setting the output voltage fb r2 r1 c f 3633 f02 v out sgnd LTC3633 applications information output voltage programming each regulators output voltage is set by an external resis- tive divider according to the following equation: v out = 0.6v 1 + r2 r 1 the desired output voltage is set by appropriate selection of resistors r1 and r2 as shown in figure 2. choosing large values for r1 and r2 will result in improved zero- load ef? ciency but may lead to undesirable noise coupling or phase margin reduction due to stray capacitances at the v fb node. care should be taken to route the v fb trace away from any noise source, such as the sw trace. to improve the frequency response of the main control loop, a feedforward capacitor, c f , may be used as shown in figure 2. minimum off-time/on-time considerations the minimum off-time is the smallest amount of time that the LTC3633 can turn on the bottom power mosfet, trip the current comparator and turn the power mosfet back off. this time is typically 40ns. for the controlled on-time control architecture, the minimum off-time limit imposes a maximum duty cycle of: dc f t max off min () () ?? = () 1 where f is the switching frequency and t off(min) is the minimum off-time. if the maximum duty cycle is surpassed, due to a dropping input voltage for example, the output will drop out of regulation. the minimum input voltage to avoid this dropout condition is: v v ft in min out off min () () ? = ? () 1 conversely, the minimum on-time is the smallest dura- tion of time in which the top power mosfet can be in its on state. this time is typically 20ns. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: dc f t min on min () () ? = () where t on(min) is the minimum on-time. as the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. in the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regula- tion, but the switching frequency will decrease from its programmed value. this constraint may not be of critical importance in most cases, so high switching frequencies may be used in the design without any fear of severe consequences. as the sections on inductor and capacitor selection show, high switching frequencies allow the use of smaller board components, thus reducing the footprint of the application circuit. internal/external loop compensation the LTC3633 provides the option to use a ? xed internal loop compensation network to reduce both the required external component count and design time. the internal loop compensation network can be selected by connec- tion the ith pin to the intv cc pin. to ensure stability it is recommended that internal compensation only be used with applications with f sw > 1mhz. alternatively, the user may choose speci? c external loop compensation components to optimize the main control loop transient response as desired. external loop compensation is chosen by simply connecting the desired network to the ith pin.
LTC3633 16 3633f applications information suggested compensation component values are shown in figure 3. for a 2mhz application, an r-c network of 220pf and 13k provides a good starting point. the bandwidth of the loop increases with decreasing c. if r is increased by the same factor that c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. a 10pf bypass capacitor on the ith pin is recommended for the purposes of ? ltering out high frequency coupling from stray board capacitance. in addition, a feedforward capacitor c f can be added to improve the high frequency response, as previously shown in figure 2. capacitor c f provides phase lead by creating a high frequency zero with r2 which improves the phase margin. (from 0.5 to 2 times their suggested values) to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of ~1s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im- mediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. when observing the response of v out to a load step, the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order over- shoot/dc ratio cannot be used to determine phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to linear technology application note 76. in some applications, a more severe transient can be caused by switching in loads with large (>10f) input capacitors. the discharged input capacitors are effectively put in paral- lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap controller is designed speci? cally for this purpose and usually incorporates current limiting, short-circuit protection, and soft starting. figure 3. compensation component ith r comp 13k c comp 220pf 3633 f03 sgnd LTC3633 checking transient response the regulator loop response can be checked by observing the response of the system to a load step. when con? gured for external compensation, the availability of the ith pin not only allows optimization of the control loop behavior but also provides a dc-coupled and ac ? ltered closed loop response test point. the dc step, rise time, and settling behavior at this test point re? ect the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the ith external components shown in figure 3 circuit will provide an adequate starting point for most applica- tions. the series r-c ? lter sets the dominant pole-zero loop compensation. the values can be modi? ed slightly
LTC3633 17 3633f mode/sync operation the mode/sync pin is a multipurpose pin allowing both mode selection and operating frequency synchronization. floating this pin or connecting it to intv cc enables burst mode operation for superior ef? ciency at low load currents at the expense of slightly higher output voltage ripple. when the mode/sync pin is tied to ground, forced continuous mode operation is selected, creating the lowest ? xed output ripple at the expense of light load ef? ciency. the LTC3633 will detect the presence of the external clock signal on the mode/sync pin and synchronize the internal oscillator to the phase and frequency of the incoming clock. the presence of an external clock will place both regulators into forced continuous mode operation. output voltage tracking and soft-start the LTC3633 allows the user to control the output voltage ramp rate by means of the trackss pin. from 0 to 0.6v, the trackss voltage will override the internal 0.6v reference input to the error ampli? er, thus regulating the feedback voltage to that of the trackss pin. when trackss is above 0.6v, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. applications information the voltage at the trackss pin may be driven from an external source, or alternatively, the user may leverage the internal 1.4a pull-up current source to implement a soft-start function by connecting an external capacitor (c ss ) from the trackss pin to ground. the relationship between output rise time and trackss capacitance is given by: t ss = 430000 ? c ss a default internal soft-start ramp forces a minimum soft- start time of 400s by overriding the trackss pin input during this time period. hence, capacitance values less than approximately 1000pf will not signi? cantly affect soft-start behavior. when driving the trackss pin from another source, each channels output can be set up to either coincidentally or ratiometrically track another supplys output, as shown in figure 4. in the following discussions, v out1 refers to the LTC3633 output 1 as a master channel and v out2 refers to output 2 as a slave channel. in practice, either channel can be used as the master. to implement the coincident tracking in figure 4a, con- nect an additional resistive divider to v out1 and connect its midpoint to the trackss pin of the slave channel. time (4a) coincident tracking v out1 v out2 output voltage 3633 f04a v out1 v out2 time 3633 f04b (4b) ratiometric tracking output voltage figure 4. two different modes of output voltage tracking
LTC3633 18 3633f applications information the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 5a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking, the feedback pin of the master channel should connect to the trackss pin of the slave channel (as in figure 5b). by selecting different resistors, the LTC3633 can achieve different modes of tracking including the two in figure 4. upon start-up, the regulator defaults to burst mode opera- tion until the output exceeds 80% of its ? nal value (v fb > 0.48v). once the output reaches this voltage, the operating mode of the regulator switches to the mode selected by the mode/sync pin as described above. during normal operation, if the output drops below 10% of its ? nal value (as it may when tracking down, for instance), the regula- tor will automatically switch to burst mode operation to prevent inductor saturation and improve trackss pin accuracy. output power good the pgood output of the LTC3633 is driven by a 15 (typical) open-drain pull-down device. this device will be turned off once the output voltage is within 5% (typical) of the target regulation point, allowing the voltage at pgood to rise via an external pull-up resistor. if the output voltage exits an 8% (typical) regulation window around the target regulation point, the open-drain output will pull down with 15 output resistance to ground, thus dropping the pgood pin voltage. this behavior is described in figure 6. figure 6. pgood pin behavior pgood voltage output voltage nominal output 0% 8% C5% 5% 3633 f06 C8% r3 r1 r4 r2 r3 v out2 r4 (5a) coincident tracking setup to v fb1 pin to trackss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 3633 f05 (5b) ratiometric tracking setup to v fb1 pin to trackss2 pin to v fb2 pin v out1 figure 5. setup for coincident and ratiometric tracking a ? lter time of 40s (typical) acts to prevent unwanted pgood output changes during v out transient events. as a result, the output voltage must be within the target regulation window of 5% for 40s before the pgood pin pulls high. conversely, the output voltage must exit the 8% regulation window for 40s before the pgood pin pulls to ground. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine
LTC3633 19 3633f applications information what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: % ef? ciency = 100% C (l1 + l2 + l3 +) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC3633 circuits: 1) i 2 r losses, 2) switching losses and quiescent power loss 3) transition losses and other losses. 1. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current ? ows through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 2. the internal ldo supplies the power to the intv cc rail. the total power loss here is the sum of the switching losses and quiescent current losses from the control circuitry. each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f is the switching frequency. for estimation purposes, (q t + q b ) on each LTC3633 regulator channel is approximately 2.3nc. to calculate the total power loss from the ldo load, simply add the gate charge current and quiescent cur- rent and multiply by v in : p ldo = (i gatechg + i q ) ? v in 3. other hidden losses such as transition loss, cop- per trace resistances, and internal load currents can account for additional ef? ciency degradations in the overall power system. transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. the LTC3633 internal power devices switch quickly enough that these losses are not signi? cant compared to other sources. other losses, including diode conduction losses during dead-time and inductor core losses, generally account for less than 2% total additional loss. thermal considerations the LTC3633 requires the exposed package backplane metal (pgnd) to be well soldered to the pc board to provide good thermal contact. this gives the qfn and tssop packages exceptional thermal properties, which are necessary to prevent excessive self-heating of the part in normal operation. in a majority of applications, the LTC3633 does not dis- sipate much heat due to its high ef? ciency and low thermal resistance of its exposed-back qfn package. however, in applications where the LTC3633 is running at high ambi- ent temperature, high v in , high switching frequency, and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off until temperature returns to 140c. to prevent the LTC3633 from exceeding the maximum junction temperature of 125c, the user will need to do some thermal analysis. the goal of the thermal analysis
LTC3633 20 3633f applications information is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera- ture rise is given by: t rise = p d ? ja as an example, consider the case when one of the regula- tors is used in an application where v in = 12v, i out = 2a, frequency = 2mhz, v out = 1.8v. from the r ds(on) graphs in the typical performance characteristics section, the top switch on-resistance is nominally 140m and the bottom switch on-resistance is nominally 80m at 70c ambient. the equivalent power mosfet resistance r sw is: r ds(on) top ? 1.8v 12v + r ds(on) bot ? 10.2v 12v = 89m from the previous sections discussion on gate drive, we estimate the total gate drive current through the ldo to be 2mhz ? 2.3nc = 4.6ma, and i q of one channel is 0.65ma (see electrical characteristics). therefore, the total power dissipated by a single regulator is: p d = i out 2 ? r sw + v in ? (i gatechg + i q ) p d = (2a) 2 ? (0.089) + (12v) ? (4.6ma + 0.65ma) = 0.419w running two regulators under the same conditions would result in a power dissipation of 0.838w. the qfn 5mm 4mm package junction-to-ambient thermal resistance, ja , is around 43c/w. therefore, the junction temperature of the regulator operating in a 70c ambient temperature is approximately: t j = 0.838w ? 43c/w + 70c = 106c which is below the maximum junction temperature of 125c. with higher ambient temperatures, a heat sink or cooling fan should be considered to drop the junc- tion-to-ambient thermal resistance. alternatively, the tssop package may be a better choice for high power applications, since it has better thermal properties than the qfn package. remembering that the above junction temperature is obtained from an r ds(on) at 70c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. redoing the calculation assuming that r sw increased 12% at 106c yields a new junction temperature of 109c. if the application calls for a higher ambient temperature and/or higher load currents, care should be taken to reduce the temperature rise of the part by using a heat sink or air ? ow. figure 7 is a temperature derating curve based on the dc1347 demo board (qfn package). it can be used to estimate the maximum allowable ambient temperature for given dc load currents in order to avoid exceeding the maximum operating junction temperature of 125c. figure 7. temperature derating curve for dc1347 demo circuit junction temperature measurement the junction-to-ambient thermal resistance will vary de- pending on the size and amount of heat sinking copper on the pcb board where the part is mounted, as well as the amount of air ? ow on the device. in order to properly evaluate this thermal resistance, the junction temperature needs to be measured. a clever way to measure the junction temperature directly is to use the internal junction diode on one of the pins (pgood) to measure its diode voltage change based on ambient temperature change. first remove any external passive component on the pgood pin, then pull out 100a from the pgood pin to turn on its internal junction diode and bias the pgood pin to a negative voltage. with no output current load, measure the pgood voltage at an ambient temperature of 25c, 75c and 125c to establish a slope relationship between the delta voltage on pgood and delta ambient temperature. once this slope is established, then the junction temperature rise can be measured as a function 0 channel 1 load current (a) 0.5 1.0 1.5 2.0 3.0 2.5 50 125 3633 f07 0 3.5 25 75 100 maximum allowable ambient temperature (c) ch2 load = 0a ch2 load = 1a ch2 load = 2a ch2 load = 3a
LTC3633 21 3633f of power loss in the package with corresponding output load current. although making this measurement with this method does violate absolute maximum voltage ratings on the pgood pin, the applied power is so low that there should be no signi? cant risk of damaging the device. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3633. check the following in your layout: 1) do the input capacitors connect to the v in and pgnd pins as close as possible? these capacitors provide the ac current to the internal power mosfets and their drivers. 2) the output capacitor, c out , and inductor l should be closely connected to minimize loss. the (C) plate of c out should be closely connected to both pgnd and the (C) plate of c in . 3) the resistive divider, (e.g. r1 to r4 in figure 8) must be connected between the (+) plate of c out and a ground line terminated near sgnd. the feedback signal v fb should be routed away from noisy components and traces, such as the sw line, and its trace length should be minimized. in addition, the r t resistor and loop compensation components should be terminated to sgnd. 4) keep sensitive components away from the sw pin. the r t resistor, the compensation components, the feedback resistors, and the intv cc bypass capacitor should all be routed away from the sw trace and the inductor l. 5) a ground plane is preferred, but if not available, the signal and power grounds should be segregated with both connecting to a common, low noise reference point. the connection to the pgnd pin should be made with a minimal resistance trace from the reference point. applications information 6) flood all unused areas on all layers with copper in order to reduce the temperature rise of power components. these copper areas should be connected to the exposed backside of the package (pgnd). refer to figures 9 and 10 for board layout examples. design example as a design example, consider using the LTC3633 in an application with the following speci? cations: v in(max) = 13.2v, v out1 = 1.8v, v out2 = 3.3v, i out(max) = 3a, i out(min) = 10ma, f = 2mhz, v droop ~ (5% ? v out ). the following discussion will use equations from the previous sections. because ef? ciency is important at both high and low load current, burst mode operation will be utilized. first, the correct r t resistor value for 2mhz switching fre- quency must be chosen. based on the equation discussed earlier, r t should be 160k; the closest standard value is 162k. rt can be tied to intv cc if switching frequency accuracy is not critical. next, determine the channel 1 inductor value for about 40% ripple current at maximum v in : l1 = 1.8v 2mhz ? 1.2 a 1 1.8v 13.2 v = 0.64 h a standard value of 0.68h should work well here. solv- ing the same equation for channel 2 results in a 1h inductor. c out will be selected based on the charge storage require- ment. for a v droop of 90mv for a 3a load step: c out1 3? i out f 0 v droop = 3?(3a) (2mhz)(90mv) = 50 f
LTC3633 22 3633f applications information a 47f ceramic capacitor should be suf? cient for channel 1. solving the same equation for channel 2 (using 5% of v out for v droop ) results in 27f of capacitance (22f is the closest standard value). c in should be sized for a maximum current rating of: ia vvv v a rms = ? () = 3 1 8 13 2 1 8 13 2 1 ... . solving this equation for channel 2 results in an rms input current of 1.3a. decoupling each v in input with a 47f ceramic capacitor should be adequate for most applications. lastly, the feedback resistors must be chosen. picking r1 and r3 to be 12.1k, r2 and r4 are calculated to be: r2 = (12.1k) ? 1.8v 0.6v C1 = 24.2k r4 = (12.1k) ? 3.3v 0.6v C1 = 54.5k the ? nal circuit is shown in figure 8. run1 run2 rt trackss2 pgood2 LTC3633 boost2 3633 f08 0.1f l2 1h r4 54.9k r3 12.1k sw2 v on2 v in2 v in1 v fb2 phmode trackss1 pgood1 boost1 sw1 v on1 v fb1 c out2 22f v out2 3.3v at 3a 0.1f l1 0.68h r2 24.3k r1 12.1k c out1 47f v out1 1.8v at 3a v in 12v c in 47f 2 r5 162k mode/sync ith1 ith2 v2p5 intv cc c2 2.2f pgnd sgnd figure 8. design example circuit
LTC3633 23 3633f figure 9. example of power component layout for qfn package applications information figure 10. example of power component layout for tssop package sw2 c boost2 c boost1 sw1 vias to ground plane vias to ground plane vias to ground plane via to boost1 via to boost2 via to v on2 /r4 (not shown) via to v on1 /r2 (not shown) v out2 gnd v in gnd v out1 sgnd (to nonpower components) 3633 f09 c out2 c in c in c out1 l2 l1 sw1 sw2 vias to ground plane vias to ground plane vias to ground plane via to boost2 via to boost1 via to v on2 and r4 (not shown) via to v on1 and r2 (not shown) v out2 v out1 sgnd (to nonpower components) 3633 f10 l1 l2 c out2 c out1 c in c in gnd gnd v in c boost1 c boost2
LTC3633 24 3633f typical applications 1.2v/2.5v 4mhz buck regulator run1 run2 rt LTC3633 boost2 3633 ta02 0.1f l2 0.82h r4 31.6k r3 10k sw2 v on2 v in2 v in1 v fb2 boost1 mode/sync sw1 v on1 v fb1 c out2 22f v out2 2.5v at 3a 0.1f l1 0.47h r2 10k r1 10k c out1 47f v out1 1.2v at 3a v in 3.6v to 15v c1 22f 2 220pf 10pf r5 80.6k ith2 v2p5 phmode 6.98k ith1 intv cc c2 2.2f 220pf 6.98k 10pf pgnd sgnd 3.3v/1.8v sequenced regulator with 6v input uvlo (v out1 enabled after v out2 ) run1 pgood2 run2 rt LTC3633 boost2 3633 ta05 0.1f l2 1h r4 54.9k r3 12.1k sw2 v on2 v in2 v in1 v fb2 boost1 sw1 v on1 v fb1 c out2 22f v out2 3.3v at 3a 0.1f l1 0.68h r2 24.3k r1 12.1k c out1 47f v out1 1.8v at 3a v in 6v to 15v c1 47f 2 r5 162k r7 154k r8 40k v2p5 ith1 ith2 intv cc c2 2.2f mode/sync phmode r6 100k pgnd sgnd
LTC3633 25 3633f typical applications 1.2v/1.8v buck regulator with coincident tracking and 6v input uvlo run1 run2 rt LTC3633 boost2 3633 ta03 0.1f l2 0.47h r4 10k r3 10k sw2 v on2 v in2 v in1 v fb2 boost1 sw1 v on1 v fb1 c out2 68f v out2 1.2v at 3a 0.1f l1 0.68h r6 4.99k r1 10k c out1 47f v out1 1.8v at 3a v in 3.6v to 15v c1 47f 2 r5 162k r7 154k r8 40k trackss2 r2 15k mode/sync ith1 ith2 intv cc c2 2.2f v2p5 phmode pgnd sgnd
LTC3633 26 3633f package description fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation eb fe2 8 (eb) tssop 0204 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 134 5 6 7 8 910 11 12 13 14 19 20 22 21 15 16 1 8 17 9.60 ? 9. 8 0* (.37 8 ? .3 8 6) 4.75 (.1 8 7) 2.74 (.10 8 ) 2 8 2726 25 24 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .011 8 ) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.1 8 7) 2.74 (.10 8 ) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
LTC3633 27 3633f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 2 8 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd2 8 ) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b)
LTC3633 28 3633f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0110 ? printed in usa related parts typical application part number description comments ltc3605 15v, 5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4v to 15v, v out(min) = 0.6v, i q = 2ma, i sd < 15a, 4mm 4mm qfn-24 ltc3603 15v, 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 4mm 4mm qfn-20, msop-16e ltc3602 10v, 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4.5v to 10v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 3mm 3mm qfn-16, msop-16e ltc3601 15v, 1.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 1a, 4mm 4mm qfn-20, msop-16e 3.3v/1.8v buck regulator with 2.5v ldo output run1 run2 rt LTC3633 boost2 3633 ta04 0.1f l2 0.68h r4 20k r3 10k sw2 v on2 v in2 v in1 v fb2 boost1 sw1 v on1 v fb1 c out2 47f v out2 1.8v at 3a 0.1f l1 1h r2 45.3k r1 10k c out1 22f v out1 3.3v at 3a 2.5v at 10ma v in c1 47f 2 r5 162k v2p5 ith1 phmode ith2 mode/sync intv cc c2 2.2f pgnd sgnd

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